`timescale 1ns/1ns
module t_SEG7_LUT;
  reg [3:0] iDIG;
  wire [6:0] OSEG;
  
  reg clock;
  
  initial
  begin
    iDIG[3:0]=4'd0;
    clock = 1'b0;
  end
  
  always #5 clock = ~clock;
  
  always @(posedge clock) 
  begin
    iDIG[3:0] = {$random}%16;
  end
  
  SEG7__LUT m1(
  .iDIG(iDIG),
  .oSEG(oSEG));
endmodule
